1. Field of the Invention
The present invention relates to a cache system, and more particularly, to a cache system capable of predicting how a cache is to be accessed according to an address.
2. Description of the Prior Art
U.S. Pat. No. 6,643,739 discloses a conventional cache system 100 as shown in FIG. 1. The conventional cache system 100 includes an address 110 having a tag field 111, an index field 112 and a word field 113, a cache 120, a plurality of comparators 130a-130n, a plurality of buffers 140a-140n, and a way prediction table 150. The operation principles for the above elements can be found by referring to U.S. Pat. No. 6,643,739. The conventional cache system 100, however, has some drawbacks; for example, addresses that have the same tag fields 111 all correspond to the same index in the way prediction table 150 since the way prediction table 150 utilizes the tag fields 111 of the addresses as the index in this cache system. Therefore, the predicted way of an accessing address A obtained from looking up the way prediction table 150 may be the previous hit way information of another accessing address B. Moreover, in order to accelerate the execution of computation, when receiving a current command from a processor, conventional cache systems access data in advance that is possibly requested by a next command according to the current command's address. Therefore, the way information stored in the way prediction table 150 is the way of the cache accessed by the next command, and is indexed by the tag field of the current command address. In this situation, if a command C received from the processor has more than two possible executing results, i.e., the address of the command C corresponds to a plurality of next commands C′ and C″ (for example, the command C is a branch instruction, and the executing results include branch taken and branch not taken), the way information corresponding to the commands C′ and C″ cannot be distinguished in the way prediction table 150 of the conventional cache system 100. As a result, the predicting accuracy of the conventional cache system 100 cannot be improved, causing insufficient power consumption of the cache system 100.